A conventional data communication system comprises a transmitter, a transmission media, and a receiver, wherein the transmission media may be named a channel in the communication field. Data are modulated to be modulated data by the transmitter. The modulated data are transmitted over the transmission media to the receiver, and then demodulated by the receiver. Non-return-to-zero (NRZ) signal is a signal as an example of modulation scheme used in a digital data communication system. In FIG. 1, a schematic waveform of an NRZ modulated signal is shown with its corresponding binary data. In the NRZ signal, a logical value 1 represents that the signal has a high voltage with a pulse width of T, and a logical value 0 represents that the signal has a low voltage also with a pulse width of T. The pulse width T is the reciprocal of the data rate. The NRZ modulated signal has both clock and data information and is thus not transmitted with a separate clock signal.
However, in telecommunication, transmission with a bandlimited channel and multipath propagation brings the phenomenon of intersymbol interference (ISI), which makes the received signal distorted in the digital transmission system, wherein the distortion is shown as a form that a single signal is temporarily scattered and then overlapped. In order to avoid the intersymbol interference, a duobinary coding having the effect of adaptive equalization and error correcting codes is used as an embodiment at the present time.
It is understood that the NRZ modulated signal with its corresponding two-level binary signal, which is converted to three-level binary signal, is considered as one of correlative-level coding schemes. Specifically, the required bandwidth can be reduced to one half of the bit rate by the duobinary coding scheme, which improves the channel transmission efficiency.
FIG. 2 illustrates a schematic diagram of the communication system with a duobinary coding scheme using the NRZ modulated signal. The communication system (such as a transceiver) 2 in FIG. 2 includes a transmitter 210, a transmission media 220, and a receiver 230. The transmitter 210 includes a precoder 212, such as an 8B10B encoder, and an equalizer, such as a feed-forward equalizer, wherein the precoder 212 is used for encoding to input the binary data to another binary data sequence.
In general, as shown in FIG. 3, the precoder 212 includes a D flip-flop 2121 functioning as a delay line and a XOR gate 2122 used for encoding. The XOR gate 2122 in the precoder 212 receives a non-return-to-zero signal Din in a form of binary digital signal and a previous digital signal W[n-1] from the D-type flip-flop 2121 to implement an exclusive-OR operation to output a current digital signal W[n] wherein the previous digital signal W[n-1] is obtained via the D flip-flop 2121 for delaying the current digital signal W[n] by a duty cycle, that is, W[n]=Din⊕W[n-1], and the current digital signal W[n], which is also called as a coded digital signal, is inputted into an input terminal D′ of the D flip-flop 2121.
A clock signal Ckin is used as a trigger signal of the D flip-flop 2121. As known, any clock signal has two edges: a rising edge and a falling edge. In one embodiment, the rising edge is used and referred to as the leading edge, while the falling edge is used and referred to as the trailing edge. In other embodiments, the falling edge is used and referred to as the leading edge, while the rising edge is used and referred to as the trailing edge. Choosing which edge of the clock to use as the leading or trailing edge is a matter of design choice.
The previous digital signal W[n-1] from the D flip-flop 2121 and the NRZ modulated signal Din are respectively inputted to the XOR gate 2122 in the precoder 2122 that implements an exclusive-OR operation to generate the coded signal W[n] that is called as the Z-transform in the signal processing field. It is understood that the Z-transform converts a discrete time-domain signal, which is a sequence of real or complex numbers, into a complex frequency-domain representation.
It is still to be explained below. Mainly, the present communication system is a linear time-invariant system, and the transfer function is a mathematical representation, in terms of spatial or temporal frequency, of the relation between the input and output of a (linear time-invariant) system.
In its simplest form for the continuous-time input signal Din(t) and the output W[n](t), the transfer function H(x) is the linear mapping of the Laplace transform of the input, Din(s), to the output W[n](s). And then the transfer function H(x) is satisfied with a Equation (1), as will be described in detail below.W[n](s)=H(s)Din(s)   Equation(1)
In the discrete-time system, the transfer function is similarly written as a Equation(2)
W[n](Z)=H(Z)Din(Z) . . . Equation(2), it is well-known that the transfer function H(Z) is the inverse transfer function of the duobinary signal, i.e., 1/(1+Z−1).
Continually, the coded signal W[n] is equalized by the feed-forward equalizer 214 and then the feed-forward equalizer 214 is used to compensate for amplitude loss, which is caused by the channel 220. Known that the feed-forward equalizer 214 is a filter, preferably, the coefficients of the feed-forward equalizer 214 can be fitly updated, so that the feed-forward equalizer 214 can shape the NRZ modulated signal from a input terminal of the feed-forward equalizer 214 to the duobinary signal from a front input terminal of the receiver 230, wherein the transfer function H(Z) from the feed-forward equalizer 214 to the channel 220 is 1+Z−1.
The coded digital signal, which is received from the front input terminal of the receiver 230 through the channel 220, is called as a three-level duobinary signal y1 (regarded as a analog signal), wherein the three-level duobinary signal y1 from the channel 220 is obtained by an Equation (3), as will be described in detail below.y1=W[n]+W[n−1]  Equation (3)
As shown in FIG. 4, it is necessary to be explained that the NRZ modulated signal Din representing “1” and “0” digital data, where Tb denotes the bit period of the signal. The NRZ modulated signal Din and the previous digital signal W[n-1] are processed through an XOR operation by the XOR gate 2122 to obtain the coded digital signal W[n], which are processed through the transfer function H(Z)=1+Z−1 to obtain the three-level duobinary signal y1. The three-level duobinary signal y1 may include the values of 1, 0 or 2 as described below in Table 1.
TABLE 1Exclusive-ORTransferInputoperationfunctionDinW[n − 1]W[n]H(z)y10001 + Z−10011210111101
Moreover, as shown in FIG. 5, the three-level duobinary signal y1 is decoded by a decode circuit 231 in the receiver 230 and the three-level duobinary signal y1 is decoded into a series of digital numbers. The digital numbers may be binary, Gray code or two's complement binary.
It is seen by those ordinarily skilled in the art that the receiver 230 in the transceiver 2 can implement a conventional three-level Flash analog-to-digital converter (ADC) including a first and a second comparators 2311 and 2312, wherein the first and the second comparators 2311 and 2312 in the decoder circuit 231 both receive the three-level duobinary signal y1 from the channel 220, and the two comparators 2311 and 2312 have their respective reference voltages ref+ and ref−. The reference voltages ref+ and ref− can be predetermined based on the voltage of the three-level duobinary signal y1 expected by the inside of the receiver 230 or set by an external circuit which is manually adjusted. The two comparators 2311 and 2312 output a two-bit comparison results (that is, each outputs a one-bit comparison result) based on their respective reference voltages, and the two-bit comparison results is decoded and recovered as one-bit digital data Dout(with the value of 0 or 1) by using a logic circuit (for example, an XOR gate).
Note that the better operation for the precoder 210 is that the NRZ modulated signal Din is aligned with the transition edge of the previous digital signal W[n-1]. In order to meet this condition, the time sum of the gate delay TXOR of the XOR gate 2122 and the output delay TD→Q for data of the D flip-flop 2121 to output therefrom is exactly equal to the bit period Tb of the NRZ modulated signal Din as seen in FIG. 4.
As explained above, in order to generate the output delay TD→Q for the data of the D flip-flop 2121, the phase difference the clock signal CKin is relative to the current digital signal W[n] needs to be maintained as a constant value. Unfortunately, when the transceiver 2 operates in a high speed, the phase difference of the clock signal CKin is relative to the current digital signal W[n] tends to drift to be difficultly controlled that makes the precoder 210 fail to operate in the high speed.
Therefore, the conventional receiver using two comparators with reference voltages, which are manually set or predetermined based on the voltage of the three-level binary signal. Under the PVT (Process, Voltage and Temperature) variation, the two comparators cannot dynamically vary the two different reference voltages, so that the three-level duobinary signal is made to occur many errors during the decoding period.
Thus, what is needed is a transceiver circuit to improve the defects from conventional transceiver in high operations or PVT variation.